Conventionally, the width of a signal pulse in a digital signal processor (“DSP”) or other integrated circuit may be modulated (i.e., varied in width) using a pulse-width modulator (“PWM”) circuit that typically includes (i) a synchronous digital counter for generating a count value and (ii) a digital comparator for comparing the generated count value with predetermined/pre-programmed threshold values. Upon detecting that the count has reached a first programmed threshold, a pulse signal (e.g., a voltage or a current signal) is generated and output to a load; the pulse signal is switched off when the comparator detects a count reaching a second programmed threshold, as depicted in FIG. 1. Accordingly, the pulse width (or step size) of the signal is modulated by the counter and the comparator.
Because the counter for conventional PWM functions at a frequency determined by the cycle time of a system clock, the resolution of the conventional PWM is limited by a single period, Tsclk, of the system clock. For example, the maximum frequency of the system clock in current DSPs is roughly 500 MHz (i.e., Tsclk=2 ns), limiting the resolution of the PWM to 2 ns. A higher resolution (for example, 150 ps), however, may be required for various applications, such as a motor controller, a switched mode power supply controller, an uninterruptible power supply and/or other power conversion applications and/or other applications of integrated circuits where Digital to Analog Converter functionality or PWM functionality is required. Creating a pulse-width resolution of 150 ps by conventional PWM approaches requires a clock frequency of at least 8 GHz; this very high frequency is infeasible, however, due to the power and implementation constraints on typical DSPs.
In one existing system, a high-resolution pulse-width modulation circuit is created based on a micro-edge positioner (“MEP”) technology that is capable of positioning an edge of the signal waveform finely on a sub-divided system clock period of a conventional PWM. The step-size (or pulse width) of the high resolution PWM waveform generated using the MEP logic, however, varies depending on the process, voltage and/or temperature of the PWM, and may thus be unreliable. Additionally, the MEP approach disadvantageously requires a periodic software calculation by the user to calibrate the MEP scale factor required to produce the high resolution PWM waveform.
Consequently, there is a need to precisely increase the resolution of the PWM by providing a constant step-size of the PWM waveform without requiring calibrations by the user.